Design Verification Engineer (Wireless Connectivity), Bhubaneswar

Boltchip is a Consulting company based out of Singapore building capability centers for next-gen computing companies in ASIA Role : Design Verification Engineer (Wireless Connectivity) Location : Bhubaneshwar. Role Overview As a Design Verification Engineer, you will be responsible for the functional verification of cutting-edge WiFi (802.11ax/be) SoCs. You will develop sophisticated constrained-random verification environments and ensure the silicon meets the highest standards of performance and reliability before tape-out.Key Responsibilities Environment Development: Build and maintain scalable, reusable UVM (Universal Verification Methodology) testbenches at the block, sub-system, and SoC levels. Test Planning: Analyze hardware specifications to create comprehensive verification plans, defining coverage goals (functional and code) and test scenarios.Verification Execution: Write and debug complex sequences, drivers, monitors, and scoreboards. Advanced Techniques: Implement Assertion-Based Verification (SVA) and functional coverage to ensure 100% verification closure. Collaboration: Work closely with Design (RTL) and Systems teams to resolve architectural bottlenecks and debug hardware/software interactions.Gate Level Simulation: Perform GLS and power-aware verification to ensure timing and power intent (UPF/CPF) are met. Desired Profile (3–8 Years Experience) For the 3-5 Year Range: Strong hands-on coding in SystemVerilog/UVM and a proven track record of closing coverage on complex blocks. You should be comfortable debugging RTL issues independently.For the 6-8 Year Range: Experience in Full-Chip/SoC verification and the ability to mentor junior engineers. You should have experience with performance verification (throughput/latency) specific to wireless data paths. Domain Knowledge: Familiarity with MAC/PHY layering, OFDM, and MIMO concepts is highly valued for a WiFi-centric role.