Layout Engineer (Telangana)

Role & responsibilities Perform full-custom analog layout for advanced nodes (28nm and below
- FinFET/CMOS technologies). Work on block-level and top-level layouts of circuits such as: PLLs, ADCs, DACs, LDOs, Bandgaps, High-speed IOs, SerDes, RF blocks. Ensure matching, symmetry, shielding, guard-ring insertion, dummy device handling and other analog layout best practices. Collaborate closely with circuit design engineers to understand design intent and implement efficient layout solutions. Handle floorplanning, device placement, routing, and parasitic-aware optimizations. Perform DRC, LVS, ERC, Antenna, and Reliability checks and work with verification teams to achieve signoff quality. Optimize layouts for IR drop, electromigration (EM), signal integrity (SI), and thermal considerations. Exposure to multi-Vt and multi-Vdd layouts, low-power techniques, and analog-mixed-signal (AMS) SoC integration. Required Skills: Strong expertise in analog/custom layout at advanced nodes (28nm). Proficiency in Cadence Virtuoso, Mentor/Calibre, Synopsys tools. Hands-on experience with TSMC advanced/lower technology nodes will be an added advantage. Hands-on experience with FinFET processes (16nm/7nm/5nm) is a robust plus. Deep understanding of layout-dependent effects (LDEs), matching techniques, and parasitic impact. Knowledge of ESD structures, latch-up prevention, and reliability requirements. Valuable communication skills and ability to interact with cross-functional global teams. Ability to work independently and deliver on aggressive schedules. Apply on Kit Job: kitjob.in/job/4nahz8