DFT (Design for Testability) Engineer — High-Speed …, Bengaluru

About Texas Instruments Texas Instruments (TI) is a global semiconductor company designing, manufacturing, and selling analog and embedded processing chips — powering everything from industrial automation to automotive safety systems worldwide. About the Team — High Speed Data Interface Product Group The High Speed Data Interface product group focuses on the development of differentiated high-speed SerDes SoCs targeted for automotive and industrial markets . There are two primary focus areas — Ethernet PHY and FPD-Link . Ethernet PHY Group: A large number of applications — like in-vehicle driver alertness monitors, steering, or accelerator control in automotive and robotic applications — require an Ethernet interface. The ubiquity of Ethernet-enabled devices allows customers to simplify connecting large numbers of devices in automotive and robotic environments. Customers expect robust performance in the presence of interference and ESD events, along with processing offload capabilities. The low-cost migration from CAN to Ethernet presents unique challenges requiring interdisciplinary skills with aggressive cost and power targets. FPD-Link Group: The proprietary FPD-Link interface addresses multi-gigabit (up to 20 Gbps) automotive and industrial sensor and display markets. Constant increase in density of electronic sensing and display content is pushing data rate (>20 Gbps) and BER performance requirements higher. Automotive functional safety requirements demand robust performance at these high data rates under challenging environments while maintaining low power consumption. The Broader Mission: As part of this product group, you will be engaged in designing solutions spanning Analog, Digital, and Signal Processing domains to mitigate impairments such as high channel loss, ESD strikes, and narrowband interference. The team implements high-performance equalization circuits (CTLE, FFE, DFE), high-speed converters (DAC, ADC), high-speed digital front-ends, signal processing algorithms, embedded microcontrollers, and high-speed interfaces for camera and display systems. The team has successfully achieved several differentiated innovations through collaborative cross-domain optimization. The entire product lifecycle — from product specification to customer and application support — is owned by the product group in Bangalore , giving each team member tremendous learning opportunity and enhanced scope to influence the global success of the product . We are looking for passionate, creative, and self-driven engineers who challenge traditional techniques and come up with innovative solutions to make a difference. Role Overview As a DFT Engineer , you are the guardian of silicon quality at scale. You will architect, implement, and validate the complete Design for Testability infrastructure for TI's high-speed automotive SerDes SoCs — ensuring every chip that reaches a vehicle or industrial system has been rigorously verified for manufacturing defects, parametric quality, and functional integrity. Your DFT decisions directly impact product reliability, yield, and automotive-grade quality. Key Responsibilities
- Architect and implement comprehensive DFT strategies for complex mixed-signal SerDes SoCs — covering digital scan, MBIST, LBIST, JTAG/IEEE 1149.1, and IEEE 1500 embedded core test
- Define and achieve fault coverage targets meeting automotive-grade quality requirements (>99% stuck-at, transition, path delay fault coverage)
- Develop and integrate scan insertion flows for large digital subsystems — including full-scan, partial-scan, and scan compression (X-Bounding, EDT, TK-Scan)
- Implement Memory Built-In Self-Test (MBIST) for embedded SRAMs, ROMs, and register files within the SoC
- Design and implement Logic BIST (LBIST) infrastructure for in-system and in-field diagnostic test capabilities — critical for automotive functional safety (ISO 26262)
- Develop ATE test programs and ATPG patterns for manufacturing test on Advantest / Teradyne platforms, optimizing for test time and coverage
- Implement IEEE 1687 (iJTAG) network for embedded instrument access and hierarchical test access across complex SoC subsystems
- Collaborate with analog design teams to define testability solutions for mixed-signal blocks — including DAC/ADC test modes, PLL characterization modes, and SerDes loopback
- Partner with physical design teams to ensure DFT-aware floorplanning, scan routing, and test clock tree implementation
- Drive DFT sign-off — validating ATPG coverage, test pattern simulation, and correlation between simulation and ATE results ✅ Required Qualifications
- Education: B.Tech / M.Tech in VLSI / Electronics / Computer Engineering
- Experience: 3–10 years of DFT engineering experience on complex digital or mixed-signal SoCs
- Strong expertise in scan insertion and scan compression (Synopsys DFT Compiler, Mentor DFTADVISOR, or equivalent)
- Proficiency in ATPG pattern generation and fault simulation (Synopsys TetraMAX, Cadence Modus, or equivalent)
- Experience with MBIST implementation and verification for embedded memories
- Working knowledge of JTAG (IEEE 1149.1) and boundary scan methodologies
- Understanding of ATE test program development (Advantest 93K, Teradyne UltraFLEX preferred)
- Familiarity with automotive DFT quality standards (zero-defect, PPM targets, AEC-Q100) Preferred / Valuable-to-Have Skills
- Experience with LBIST implementation for automotive functional safety (ISO 26262 ASIL-B/D)
- Knowledge of IEEE 1687 (iJTAG) for embedded instrument access
- Background in mixed-signal DFT — analog test modes, loopback testing, SERDES BIST
- Familiarity with test compression techniques (EDT, Tessent Streaming Scan Network)
- Experience with in-system test and diagnosis for automotive field applications
- Exposure to advanced node DFT challenges (FinFET, cell-aware fault models) What Makes This Role Unique Apply on Kit Job: kitjob.in/job/4n96ij