Design verification engineer - Malaysia (Mysuru)

Hi All,

Looking for Design Verification Engineer with UVM and Verilog experience.

- Good understanding of verification concepts and techniques. Very valuable knowledge of Verilog/System Verilog and UVM.
- Experience and knowledge in Verification of IP’s related to different applications. Good Knowledge in Power aware verification and Gate level verification is preferable. Should be able to understand the Full-chip Verification requirements as well and good knowledge in industry standard protocols.
- Verification for complex IP’s and close the Verification to the challenging milestones.
- Strong knowledge of AXI4/AXI5 protocol

Please forward your resume to

Regards,

Jaya Apply on Kit Job: kitjob.in/job/4n6f8n