DFT Manager (Chittoor)

Lead DFT Engineer / DFT Manager Job Title: Lead DFT Engineer / DFT Manager Company: Nesa Software Pvt Ltd Location: Bangalore Experience: 10–15 Years Employment Type: Full time Work Mode: Onsite Notice Period: Up to 60 Days Salary: No Barrier for the Right Candidate Job Summary Nesa Software Pvt Ltd is looking for an experienced and highly skilled Lead DFT Engineer / DFT Manager to drive DFT strategy, implementation, and delivery for complex SoC and IP development programs. The ideal candidate should possess deep hands-on expertise in Design for Testability (DFT), strong leadership capabilities, and experience managing cross-functional teams. This role involves technical ownership of DFT architecture, execution, signoff, and silicon validation while ensuring successful project delivery and team development. Key Responsibilities1. DFT Architecture & Strategy
- Lead end-to-end DFT architecture, implementation, and signoff for complex SoC and IP programs.
- Define and own DFT strategies including Scan Architectures, JTAG/iJTAG, Boundary Scan (BSCAN), ATPG, and MBIST.
- Review and approve DFT plans, test architectures, and test coverage targets.
- Establish and enhance DFT methodologies, automation flows, and best practices. 1. DFT Implementation & Signoff
- Drive ATPG generation, MBIST implementation, DFT simulations, and signoff activities.
- Ensure high-quality DFT implementation and achievement of test coverage goals.
- Perform DFT simulation, debug, and validation at RTL and gate-level stages.
- Manage DFT quality metrics, test coverage analysis, and signoff reviews. 1. Silicon Bring-up & Yield Improvement
- Lead silicon bring-up, failure analysis, and debug activities from a DFT perspective.
- Drive yield improvement initiatives through test data analysis and root cause identification.
- Collaborate with validation and product engineering teams to resolve silicon issues. 1. Team Leadership & Project Management
- Manage and mentor a team of DFT engineers through technical guidance, reviews, and task allocation.
- Track project schedules, milestones, and delivery commitments.
- Drive risk identification, mitigation planning, and execution for DFT deliverables.
- Ensure timely completion of DFT activities across multiple projects. 1. Cross-Functional Collaboration
- Conduct design and DFT reviews with Design, Physical Design, Validation, Product Engineering, and Management teams.
- Collaborate closely with stakeholders to align DFT requirements with project objectives.
- Interface with customers and management teams to provide DFT status updates, issue resolutions, and project plans. Technical Skills & Qualifications
- B.Tech / M.Tech in Electronics, VLSI, or a related field.
- 10–15 years of experience in Design for Testability (DFT) for SoC/IP development.
- Strong hands-on expertise in:
- JTAG / iJTAG
- Boundary Scan (BSCAN)
- Scan Architectures (Full Scan, Scan Compression, Hierarchical DFT)
- ATPG (Stuck-at, Transition, At-Speed Testing)
- MBIST and Memory Test Architectures
- DFT Simulation and Debug (RTL and Gate-Level)
- Strong understanding of:
- SoC Test Architecture
- Test Coverage Analysis
- Test Quality Metrics
- DFT Signoff Methodologies
- Experience with industry-standard DFT tools from Synopsys, Cadence, Siemens, or equivalent EDA vendors. Leadership & Management Skills
- Proven experience as a DFT Team Lead, Technical Lead, or DFT Manager.
- Demonstrated success in mentoring and leading engineering teams.
- Experience owning technical reviews, signoff processes, and project deliverables.
- Strong stakeholder management and cross-functional collaboration skills.
- Ability to drive technical decisions and resolve complex DFT challenges.
- Excellent communication, leadership, and project management abilities. Preferred Candidate
- Experience with low-power DFT methodologies.
- Expertise in IJTAG networks and advanced test compression techniques.
- Experience handling multiple SoCs or large-scale semiconductor programs.
- Customer-facing experience and program leadership responsibilities.
- Strong background in DFT methodology development and automation. Salary No salary constraints for highly qualified candidates. Compensation will be based on experience, technical expertise, and leadership capabilities. How to Apply Interested candidates may submit their resume to 75938 33665. Pay: ₹10,101,101.00
- ₹101,010,101.00 per month Work Location: In person Apply on Kit Job: kitjob.in/job/4n6w1x