Asic Rtl Design Engineer (Noida)

Position: ASIC RTL Design Engineer Experience: 8+ Years Location: Noida Share resume on medha.gaur@ Key Responsibilities
- Develop synthesizable RTL from micro-architecture specifications.
- Design digital blocks such as control logic, datapath, and bus interfaces (AXI/AHB/APB).
- Debug and validate RTL using simulation and waveform analysis.
- Collaborate with verification teams for functional validation.
- Support RTL synthesis, timing closure, and integration at So C level.
- Maintain design documentation. Required Skills
- Robust digital design fundamentals.
- Experience in Verilog/System Verilog RTL coding.
- Knowledge of AMBA protocols (AXI/AHB/APB).
- Familiarity with synthesis, lint, and CDC tools. Good debugging and problem-solving skills. Apply on Kit Job: kitjob.in/job/4md3we