R&D Engineering, Staff Engineer (VIP verification), Noida

Expertise in UVM and System Verilog. Experience in verification IP modeling with knowledge of test case coding, scoreboard design, assertions, checkers&functional coverage. Involved&played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol. Job Responsibilities: Able to contribute to the development of the VIP.Responsible&can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology