TCS Virtual Interview_Analog Mixed-Signal (AMS) Verification …, Hojai

Analog Mixed-Signal (AMS) Verification Engineer
- Experience Range: 3 to 15+ Years Location: Bangalore / Hyderabad / Noida / Ahmedabad/ Chennai/ Mumbai/ Pune Role Overview The Analog Mixed-Signal (AMS) Verification Engineer is responsible for functional, performance, and robustness verification of analog and mixed-signal IPs, subsystems, and SoCs. The role bridges analog and digital domains using mixed-signal simulation, behavioral modeling, assertions, coverage, and post-silicon correlation to ensure first-pass silicon success. The engineer works closely with analog designers, digital verification teams, layout, and silicon validation teams. Core Responsibilities (All Levels)
- Develop and execute AMS verification plans for IP, subsystem, and SoC levels
- Build mixed-signal verification environments combining analog and digital domains
- Develop behavioral models using Verilog-AMS, Wreal, or real-number modeling (RNM)
- Run and analyze mixed-signal simulations for functionality, timing, and performance
- Validate PLL lock, jitter, noise, power-up/down behavior, and corner sensitivity
- Collaborate with analog and digital teams to debug cross-domain issues
- Support post-layout, post-silicon validation, and silicon-to-simulation correlation
- Automate regressions, analysis, and reporting using scripts Senior AMS Verification Engineer
- 3 to 5 Years
- Execute block-level AMS verification under guidance
- Run mixed-signal simulations for basic AMS IPs such as comparators and bandgaps
- Assist in developing Verilog-AMS / Wreal models for analog blocks
- Analyze waveforms and debug functional issues
- Support regression runs and basic coverage collection Lead AMS Verification Engineer
- 6 to 9 Years
- Own IP or subsystem-level AMS verification from plan to signoff
- Architect mixed-signal verification environments using SV/UVM with AMS integration
- Develop assertions, checkers, and functional coverage for AMS behaviors
- Verify performance metrics such as jitter, phase noise, lock time, INL/DNL, and PSRR
- Work closely with analog designers on debug and design trade-offs
- Support low-power, multi-mode, and post-layout verification activities Member Technical Staff / Principal AMS Verification Engineer
- 10+ Years
- Define AMS verification strategy and methodology for complex SoCs
- Own full-chip AMS verification and signoff across PVT and stress scenarios
- Drive development of reusable AMS frameworks and robust behavioral models
- Lead silicon bring-up support and silicon-to-simulation correlation efforts
- Guide cross-domain debug involving analog, digital, and system interactions
- Mentor AMS verification engineers and review verification quality
- Interface with customers, architects, and EDA vendors on AMS verification topics Tools & Skills
- AMS Simulation: Cadence Xcelium AMS, Spectre, AMS Designer
- Modeling: Verilog-AMS, Wreal, Real Number Modeling (RNM)
- Digital Verification: SystemVerilog, UVM, UVM-AMS (as applicable)
- Domains: PLL, SerDes, DDR PHY, ADC/DAC, LDO, Bandgap
- Post-Silicon: Lab data analysis, silicon correlation
- Automation & Analysis: Python, MATLAB Education B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI, or Microelectronics Engineering Kind Regards, Priyankha M Apply on Kit Job: kitjob.in/job/4l9z4e