Standard Cell R&D Manager, Raniganj

What You ll Be Doing: Designing and validating custom standard cells, including flip flops, clock gating cells, level shifters, and power gating cells. Optimizing standard cell circuits to achieve better performance, power, and area (PPA). Engaging in hands-on development while mentoring and coaching junior R&D engineers. Collaborating with layout designers to optimize layout parasitics and achieve target PPA. Involving in layout extraction and understanding layout-dependent parameters in the extracted netlist. Implementing, testing, and analyzing circuit design guidelines and methodologies. The Impact You Will Have:Driving innovations in standard cell design that contribute to the success of Synopsys products. Enhancing the performance, power, and area (PPA) of our silicon IP portfolio. Mentoring and developing the next generation of R&D engineers. Collaborating across functions to ensure methodology alignment and optimization. Contributing to the continuous improvement of circuit design methodologies. Supporting the integration of more capabilities into System-on-Chip (SoC) designs, meeting unique performance, power, and size requirements.What You ll Need: Bachelors or Masters degree in Electrical Engineering or a related field. 10+ years of experience in standard cell library design. Deep understanding of CMOS device characteristics and submicron process nodes. Experience with FINFET/GAA technologies and high sigma variation analysis.Familiarity with layout design and optimization of layout parasitics.