Principal Engineer, Physical Design Yelahanka
Principal Engineer, Physical Design Yelahanka
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Yelahanka, India -
Posted: less than a week ago
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Description
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Key Responsibilities
Lead end-to-end RTL-to-GDSII execution for a given SoC program, driving synthesis, floorplanning, placement, CTS, routing, and signoff to achieve predictable tapeouts.
Owned timing, power, and physical signoff strategy, including STA, SI, IR/EM analysis, ensuring first-pass silicon success and high design reliability.
Established and enforced DRC/LVS closure methodologies, led physical verification, and streamlined ECO flows to meet aggressive tapeout schedules.
Partnered with RTL, DFT, packaging, and system teams to align design, testability, and manufacturability goals across the product lifecycle.
Defined and deployed automated design methodologies using TCL, Python, and Perl; collaborated with CAD teams to improve flow efficiency and scalability.
Championed low-power design strategies (UPF/CPF), enabling power-effective architectures aligned with product requirements.
Position Requirements
Education: B.Tech/M.Tech (or higher) in Electrical/Electronics Engineering or related field.
Experience: 12+ years in physical design with a proven track record of successful tapeouts of complex, high-performance SoCs across advanced nodes (28nm, 22nm, 16nm, 10nm, 5nm and below).
Technical Expertise: Deep expertise in full-chip physical design, including floorplanning, power planning, placement & routing, clock architecture/CTS, extraction, and full signoff methodologies.
Automation & CAD Collaboration: Proficiency in TCL, Python, or similar scripting, with a track record of driving automation and partnering with CAD teams for flow enhancements.
Cross-functional Influence: Robust collaboration with RTL, DFT, packaging, product, and system teams to align on design, test, and manufacturing goals.
Communication & Stakeholder Management: Excellent communication skills with the ability to operate effectively in global, cross-functional environments.
Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days Apply on Kit Job: kitjob.in/job/4mfudk
Key Responsibilities
Lead end-to-end RTL-to-GDSII execution for a given SoC program, driving synthesis, floorplanning, placement, CTS, routing, and signoff to achieve predictable tapeouts.
Owned timing, power, and physical signoff strategy, including STA, SI, IR/EM analysis, ensuring first-pass silicon success and high design reliability.
Established and enforced DRC/LVS closure methodologies, led physical verification, and streamlined ECO flows to meet aggressive tapeout schedules.
Partnered with RTL, DFT, packaging, and system teams to align design, testability, and manufacturability goals across the product lifecycle.
Defined and deployed automated design methodologies using TCL, Python, and Perl; collaborated with CAD teams to improve flow efficiency and scalability.
Championed low-power design strategies (UPF/CPF), enabling power-effective architectures aligned with product requirements.
Position Requirements
Education: B.Tech/M.Tech (or higher) in Electrical/Electronics Engineering or related field.
Experience: 12+ years in physical design with a proven track record of successful tapeouts of complex, high-performance SoCs across advanced nodes (28nm, 22nm, 16nm, 10nm, 5nm and below).
Technical Expertise: Deep expertise in full-chip physical design, including floorplanning, power planning, placement & routing, clock architecture/CTS, extraction, and full signoff methodologies.
Automation & CAD Collaboration: Proficiency in TCL, Python, or similar scripting, with a track record of driving automation and partnering with CAD teams for flow enhancements.
Cross-functional Influence: Robust collaboration with RTL, DFT, packaging, product, and system teams to align on design, test, and manufacturing goals.
Communication & Stakeholder Management: Excellent communication skills with the ability to operate effectively in global, cross-functional environments.
Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days Apply on Kit Job: kitjob.in/job/4mfudk
Highlights
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Company nameAnalog Devices -
Job positionPrincipal Engineer, Physical Design Yelahanka
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